An Optimized Fir Filter Implementation Using High Speed Compressors and Counter
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Multipliers, which are widely involved in various digital signal processors, are the essential elements in computer arithmetic. In a variety of computing applications, high-speed multipliers are becoming more popular. Approximate computing had given a lot of attention as a promising paradigm for minimizing power consumption, delay and area with increasing the accuracy. There are three steps to multiplication: (i) Creating partial product (PPs), (ii) Diminishing partial product and (iii) Calculation of result . Compressors minimize number of PPs stages of multipliers with more critical path delay, whereas adders require more stages to reduce partial product reduction. Counters have been used to get partial products in the multiplication process with lower critical path delay in the proposed work. Counters adds the partial product without using the previous carry signal, so it is considerably faster than traditional adders and compressors. The code is written in VERILOG, then simulated with MODELSIM and result is synthesized in Xilinx 14.2 ISE.