Distributed Arithmetic Mechanization of Multiply and Accumulate Core for DSP Applications

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Bharathi.M , Dr. Yasha Jyothi M Shirur


This paper presents a new method for constructing a Multiply and Accumulate Unit core for Distributed Arithmetic applications in Digital Signal Processing. In applications involving digital signal processing, the MAC FIR filter core is crucial. DSP functionalities in FPGA and ASIC devices benefit from the high-speed advantages of distributed arithmetic-based MAC cores. It is an effective technique that is used to compute the inner products when creating incredibly effective MAC Cores. In this article, two models based on distributed arithmetic with seven different adders are given. These models are made for varying levels of delay and area parameters. The suggested designs are implemented in XILINX ISE and xc3s1200e-5fg320 FPGA devices based on Spartan 3E. The effectiveness of the various models is assessed and shown to be superior to the state-of-the-art of traditional technique for high speed applications. Additionally, it is demonstrated that the two models that are suggested, which use different adders, speed up processing compared to earlier studies while simultaneously achieving notable increases in power and number of slice resources.

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